A 100-180-GHz InP Distributed Frequency Doubler with 11.5 dBm Peak Output Power Using a Power-Bandwidth Enhancement Technique

This paper presents a wideband distributed frequency doubler (DFD) operating from 100 to 180 GHz, generating an output power from 11.5 to 8.5 dBm. To achieve a flat response over the entire 3-dB output power bandwidth, we developed a push-push doubler core using triple-stacked HBTs and equalizing capacitors. The new equalizing capacitors improve the doubler's input line loss, allowing the use of more cores and larger transistor sizes for higher second harmonic generations at high frequencies. In the meantime, stacked HBTs enlarge the voltage swings at the cores' outputs, and the output transmission line combines the high swings across a wide bandwidth. The fabricated DFD demonstrates a peak output power of 11.5 dBm at 167 GHz, a 3-dB power bandwidth of 80 GHz, and a fractional power bandwidth of 57.1%. Up to 190 GHz, the conversion gain is higher than −4 dB, with a peak of −1 dB at 140 GHz. The chip size is 0.94 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the total power consumption is 277 mW.