Design of a RISC-V Based Hybrid Encryption Coprocessor for Resource-Constrained Environments

With the rapid advancement of electronic information technology, data security has become increasingly critical. While hybrid encryption provides higher security compared to traditional single encryption methods, its computational complexity leads to significantly higher resource consumption, making it challenging to deploy in resource-constrained environments. To address this challenge, we propose a RISC-V based hybrid encryption coprocessor designed for the SM2 and SM4 algorithms, achieving an efficient balance between resource utilization and performance. Through custom instruction set design and hardware/software co-optimization, the proposed coprocessor improves both resource efficiency and computational performance while enabling hybrid cryptographic operations. To validate the correctness and efficiency of the design, the coprocessor was integrated with the RISC-V processor and implemented on the Xilinx ZYNQ7020 FPGA. Experimental results show that, the proposed SM2 point multiplication operation achieves an 86.1% reduction in cycle count and a 28.5% decrease in resource consumption, while the SM4 implementation reduces hardware resource usage by 69.3%. These improvements highlight the effectiveness of the proposed design in enhancing the feasibility of hybrid encryption in resource-constrained environments.