A Configurable Piecewise-Linear Approximation Squarer with Unbiased Error Compensation for Energy-Efficient Floating-Point Computing
Approximate computing has emerged as a promising paradigm to enhance energy efficiency in applications where strict computational accuracy is not essential. In this work, we propose PAS, a piecewise-linear approximate floating-point squarer with unbiased error compensation and runtime configurability. PAS employs linear interpolation to iteratively approximate the square function, achieving configurability through multi-level error compensation. To optimize performance, we design a multi-level, parallelizable circuit architecture that relies solely on negation and shifting operations, significantly reducing hardware complexity. Additionally, we introduce a runtime-configurable tree structure that dynamically adapts to varying precision requirements, making PAS highly versatile for diverse application scenarios. Compared to state-of-the-art approximate squarers and multipliers, PAS achieves a superior balance between accuracy and resource efficiency. Experimental results demonstrate that PAS significantly reduces errors, with improvements of over 30% in MAE and 53% in MSE compared to existing designs, while also reducing area-delay product (ADP) by 1342%. Application-level evaluations, such as in square-law demodulation (SLD), further validate PAS’s effectiveness, showing that it achieves the best signal-to-noise ratio (SNR) and Euclidean distance performance, even when compared to exact squarers. These results highlight PAS as a highly efficient and adaptable solution for energy-constrained applications requiring approximate squaring operations.
Authors
- Cheng Zhuo (ORCID: https://orcid.org/0000-0002-2610-7522)
- Chenyi Wen (ORCID: https://orcid.org/0000-0002-6508-2639)
- Haonan Du (ORCID: https://orcid.org/0009-0003-6345-8991)
- Yingde Li (ORCID: https://orcid.org/0000-0002-4871-1421)
- Wenjing Huang (ORCID: https://orcid.org/0000-0003-1558-3571)
Institutions
- Zhejiang University (CN)
Publication Details
- Published
- 2025-05-09
- DOI
- https://doi.org/10.1109/iseda65950.2025.11100310
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00