ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA’s utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA’s scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

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Publication Details

Published
2025-05-09
DOI
https://doi.org/10.1109/iseda65950.2025.11101194
Citations
2
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
1.46

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article

ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

Zhufei Chu, Lingwei Yan, Yunhao Zhou, Lingfeng Zhou et al.
2 citations
VLSI and FPGA Design Techniques
1.46
article

ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA

Zhufei Chu, Lingwei Yan, Yunhao Zhou, Lingfeng Zhou, Chengyu Ma, Fan Yang, Ziyang Zheng, Gang Chen, Wentao Jiang, Qiang Xu, Guangyu Sun, Zhengyuan Shi, Zhiqiang He, Chuan Shi, Xiaoyan Yang, Kezhi Li, Jiawei Liu, Jiayíng Zhu, Zeju Li, Chenhao Xue, Hongyang Pan, Jun Yang
article en
2 citations

Abstract

We introduce ForgeEDA, an open-source comprehensive circuit dataset across various categories. ForgeEDA includes diverse circuit representations such as Register Transfer Level (RTL) code, Post-mapping (PM) netlists, And-Inverter Graphs (AIGs), and placed netlists, enabling comprehensive analysis and development. We demonstrate ForgeEDA’s utility by benchmarking state-of-the-art EDA algorithms on critical tasks such as Power, Performance, and Area (PPA) optimization, highlighting its ability to expose performance gaps and drive advancements. Additionally, ForgeEDA’s scale and diversity facilitate the training of AI models for EDA tasks, demonstrating its potential to improve model performance and generalization. By addressing limitations in existing datasets, ForgeEDA aims to catalyze breakthroughs in modern IC design and support the next generation of innovations in EDA.

Ningbo University (CN), Beijing University of Posts and Telecommunications (CN), Chinese University of Hong Kong (HK), Peking University (CN), Shanghai Fudan Microelectronics (China) (CN), Hangzhou Dianzi University (CN), Southeast University (CN), Nanjing University of Aeronautics and Astronautics (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 16%
VLSI and FPGA Design Techniques
1.46
DOISourceOpenAlex
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