An 86-90 GHz Adaptive Gain CMOS LNA with Linearity Enhancement & −6 dBm Blocker Tolerance

This paper presents a W-band adaptive gain lownoise amplifier to improve its IM3 rejection and blocker tolerance. The proposed design employs a current steering topology controlled by the adaptive bias (ADB) circuit and a novel coupler design for automatic gain control. The measurement results demonstrate a peak gain of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 4. 5 ~ d B}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{8 8}$</tex> GHz with a dynamic gain control range of 13 dB and constant center frequency. The minimum measured NF is 7.6 dB at 88 GHz and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&lt;9.2 ~\text{dB}$</tex> at the frequency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$86-90 \text{GHz}$</tex>. Two-tone test measurements show 10 dB improvement in IM3 rejection, and the blocker test shows <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 5} \mathbf{~ d B}$</tex> improvement in SFDR compared to the LNA with the adaptive gain turned off. The chip was fabricated in TSMC 65 nm CMOS, occupies a core area of 0.11 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{m m}^{\mathbf{2}}$</tex>, and consumes DC power of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3 7. 2 ~ m W}$</tex> when ADB is off and 40.8 mW when ADB is on.