An 8-12.2GHz CMOS Low-Noise Amplifier with Partially Tail-Coupled Transformer and Large-Transistor Achieving 1.8 dB Average NF

This paper presents an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8-12.2 \text{GHz}$</tex> low-noise amplifier (LNA) featuring a partially tail-coupled transformer and a large-transistor design to enhance noise and gain performance. The proposed partially tail-coupled transformer and large-transistor technique provides wideband input matching and a low noise figure (NF) without requiring a gate-series inductor, simplifying the design and minimizing noise degradation. To validate the design, a two-stage LNA was implemented using <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$65-\text{nm}$</tex> bulk complementary metal-oxide-semiconductor (CMOS) technology. Measurements show a peak gain of 28.5 dB and an average gain of 27.1 dB, along with a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3-\text{dB}$</tex> bandwidth of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8-12.2$</tex> GHz, and a minimum NF of 1.61 dB with an average NF of 1.8 dB across the band. The LNA achieves an IP <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${ }_{1 ~\text{dB}}$</tex> of −28.2 dBm, IIP <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$_{3}$</tex> of −19 dBm at 12 GHz, dissipates 22 mW from a 1 V supply, and occupies a compact core area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.187 ~\text{mm}^{2}$</tex>.