A 280 GHz Sub-Harmonic Injection Locked Oscillator in 45 nm CMOS PD SOI

A 280 GHz sub harmonic injection locked oscillator implemented in 45 nm RFE technology is presented. It consists in a single to differential buffer, a frequency doubler and a core triple-push oscillator. The output power on 50Ω load is -1 dBm at 280 GHz and remains constant across the oscillator 4 % tuning and locking range. The circuit, implemented in a 45 nm partially depleted CMOS process, consumes 75 mW resulting in a record 1% DC-to-RF efficiency for CMOS technologies. The injection locked phase noise is as low as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-110 \text{dBc} / \text{Hz}$</tex> at 1 MHz offset. This compact oscillator (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.4 \times 0.55 \text{mm}$</tex>) is intended to be integrated with on-chip antennas in an arrayed arrangement, resorting in an efficient source for sub-THz imagery and radcom aplications.