A 71—86-GHz Receiver with 5-GHz if Signal Bandwidth for E-Band Broadband Communication in 65-NM CMOS

This paper presents a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$71-86-\text{GHz}$</tex> receiver (RX) with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-\text{GHz}$</tex> IF bandwidth (BW) in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$65-\text{nm}$</tex> CMOS, which can be applied to high-speed and large-capacity wireless communications. The proposed receiver integrates a low-noise amplifier (LNA), a down-conversion mixer, and a baseband (BB) circuit that utilizes a mutually-coupled inductive load for wideband IF. Measurements show the receiver achieves a maximum conversion gain (CG) of 28 dB and a minimum single-sideband noise figure (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{NF}_{\text {ssb }}$</tex>) of 6.5 dB at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$77-\text{GHz}$</tex>. The measured error vector magnitude (EVM) is less than -34 dB for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.6 ~\text{Gb} / \mathrm{s} 64-\text{QAM}$</tex> signals. The receiver occupies a chip area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.45 \times 1.09 ~\text{mm}^{2}$</tex> with power consumption of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 2 3. 4 ~ m W}$</tex>.