New Approach for Aging Assessment of Digital Circuits Featuring Systematic Signal Probability Tracing

Digital circuit reliability is increasingly challenged by aging effects, particularly Bias Temperature Instability (BTI), which gradually shifts threshold voltages, degrades key electrical parameters, and exacerbates timing violations. To address these challenges, this paper proposes a systematic and efficient methodology for digital circuit aging assessment which is fully compatible with existing design flows. Our approach introduces a two-tiered framework that first derives cell-level signal probabilities (SP) from circuit-level analysis, and then leverages cell-level SPs to evaluate device-level BTI per cell. By utilizing an accelerated algorithm that derives cell-level SP directly from the synthesized netlist, our method eliminates dependence on simulation tools, thereby reducing the overall run-time and greatly improving the efficiency of aging assessment. Through a graph-based algorithm, device BTI per cell is determined and this process is integrated into the aging library characterization flow. Furthermore, our iterative technique for sequential cells efficiently resolves SP calculation problems of feedback loops, allowing accurate SP calculation throughout the entire design. Experimental results on the ISCAS85 and EPFL benchmarks demonstrate an average runtime speedup of 18.44x while verifying the correctness of the proposed method on simple benchmark circuits. Moreover, the runtime advantage becomes even more pronounced for larger-scale circuits.