Pre-Silicon Power Side-Channel Leakage Assessment Through Quantitative Information Flow Analysis

Power side-channels can cause leakage of cryptographic keys and pose a significant threat to hardware security. Although post-silicon power side-channel analysis methods are generally effective in leakage assessment, discovering side-channels after fabrication is too late, since security vulnerabilities in chips are difficult to eliminate or patch. This work aims to develop a pre-silicon power side-channel leakage assessment method that allows the evaluation of power leakage in the early hardware design and verification stages through quantitative information flow analysis. The key observation is that the distribution of taint labels can reveal power consumption characteristics. The paper constructs fine-grained precise information flow models (IFM) for cryptographic hardware designs for calculating taint labels. It further employs Shannon entropy to measure the distribution of taint labels related to secret key bits and quantify power side-channel leakage. Experimental results using AES and SM4 core designs show that our method can precisely identify modules with power side-channel security vulnerabilities and quantitatively assess the degree of leakage.