A Novel VLSI Clock Tree Synthesis Method Based on Manhattan Ring Clustering

Clock tree synthesis aims to construct a low-skew, low-power, and low-latency clock network in VLSI design flow. Different skew control techniques can affect power consumption and latency performance. Non-tree methods control skew by inserting additional buffers, leading to high power consumption. Tree-based methods usually control skew with complex routing designs, introducing extended path length and increased latency.In this paper, we propose a Manhattan-Ring clustering based clock tree synthesis method. Our method controls skew with few buffers and simple routing for power and latency reduction. First, we observe that those registers located in the same Manhattan ring can be connected to the buffers at particular positions, with low skew and simple routing. So we cluster these registers together, decide buffer positions, and drive registers with few buffers. Second, we perform a top-down topology construction from clock source to each buffer of clusters for latency control. Experimental results show that, compared with Bst&K-Means method, under the same bounded skew constraint, maximum latency is reduced by 50.3%, and buffer count is reduced by 58.3%.