A 0.9 pJ/Bit 56Gb/s High-Swing Tri-Mode Wireline Transmitter with 6-Bit DAC Controlled Tailless-CML Driver and Impedance Calibration Loop

This paper presents a tri-mode (PAM4, NRZ, Duobinary) transmitter which employs a tailless CML driver with an impedance calibration loop for achieving low power consumption and a high output swing, supporting a data rate up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$56 ~\text{Gb} / \mathrm{s}$</tex> PAM4. The proposed DAC-controlled driver is capable of supporting a wide range of swing adjustments and achieving a high-resolution adjustable FFE. By introducing an impedance calibration loop with the assistance of an off-chip reference resistor, the transmitter is capable of mitigating the impedance mismatch under a high output swing caused by the utilization of tailless CML drivers. Fabricated and tested in 28 nm CMOS process, the proposed transmitter with a total chip area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.536 \text{mm}^{2}$</tex> exhibits a power efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.9\text{pJ}/\text{bit}$</tex> and a vertical eye opening of 83 mV operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$56 ~\text{Gb} / \mathrm{s}$</tex> PAM4 under a -6 dB insertion loss condition.