FLPlace: Macro Placement with Forward-Looking Wire Mask Guidance

The development of Very Large Scale Integration (VLSI) technology has introduced new challenges for Electronic Design Automation (EDA) in chip placement. Macro placement is a crucial subproblem in the placement process, focused on determining the positions of all macros to minimize halfperimeter wire length (HPWL) while avoiding overlaps. Recently, wire-mask-guided macro placement methods have shown the potential to achieve promising results for macro placement. However, these methods are prone to getting stuck in local optima, as they focus solely on selecting the current optimal position for placing a macro. In this paper, we proposed a wiremask-guided macro placement method called FLPlace. Firstly, we presented a forward-looking wire-mask-guided algorithm that accounts for the impact of the current macro’s position on subsequent macros, thus optimizing the overall layout. Secondly, we introduced a heuristic space exploration strategy to enhance optimization efficiency. Experimental results on the ISPD2005 and ariane benchmark demonstrate that FLPlace outperforms the wire-mask-guided method WireMask-Bbo, achieving an 11.71% optimization in HPWL and converging to a high-quality solution more rapidly.