ThorSim: Throughput-Oriented Timing Simulation of FinFET Digital Circuits

Accurate timing analysis is crucial for design and verification. In addition, high throughput and scalability are mandatory for simulation-based approaches, which must often cope with high input data volumes and a high number of large circuit instances. Existing approaches using a binary switch model offer an excellent trade-off between accurate SPICE and high-performance gate level simulation in planar CMOS. However, recent experiments have shown that the binary switch model is not accurate enough for FinFET technology. The new approach presented in this paper integrates an enhanced switch-level model into an efficient GPU-based simulation flow. A high throughput is achieved by avoiding event-driven control at the top level, enabling the thread-parallel processing of independent components and input patterns. Experimental results confirm that the new approach accurately predicts the timing of digital circuits in modern CMOS technologies and scales well to multi-million transistor designs.