A >22 GS/s, 44 dB SNDR Wideband 4x4 Time-Interleaved Sampling Front-End with Bulk-Driven Mismatch Calibration in 22 nm FDSOI

This paper presents an ultra-wideband time-interleaving (TI) front-end (FE) sampler in 22nm FDSOI CMOS. It includes an isolating FE buffer driving 4 time-interleaved samplers and 2nd-level buffers operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathrm{s}} / 4$</tex>, each feeding 4 sub-Track and Holds (T&H) at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathrm{s}} / 16$</tex>. A low-jitter multi-phase on-chip clock generator (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\sigma_{\text{rms}} \approx 40 \text{fs}$</tex>), fed by a single differential reference clock, supports sampling speeds up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$32 \text{GS} / \mathrm{s}$</tex> resulting in an SNR of 48 dB at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\text{in}}=16 \text{GHz}$</tex>. The FE incorporates on-chip TI time-skew and bandwidth mismatch calibration, while gain and offset mismatches are digitally calibrated off-chip. It achieves a peak SFDR of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$54 / 49 \text{dBc}$</tex> and SNDR of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$46 / 44 \text{dB}$</tex> for low and Nyquist frequencies at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathrm{s}}=22 \text{GS} / \mathrm{s}$</tex>, while maintaining SFDR/SNDR above <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$38 / 35 \text{dB}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{\mathrm{s}}=32 \text{GS} / \mathrm{s}$</tex> up to Nyquist. The on-chip time-skew calibration improves the SFDR by up to 16 dB. In addition, a novel bulk-node calibration technique addressing bandwidth mismatch is tested. The sampler operates from a triple supply (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.2 \mathrm{V} / 0.9 \mathrm{V} /-0.6 \mathrm{V}$</tex>), consuming only 116 & 142 mW at 22 & 32 GS / s, respectively.