S-Parameter-Based Simulation Technique and Crosstalk Suppression for Large-Scale Superconducting Quantum-Computing Chip Design

The increasing size of superconducting quantumcomputer chips requires a shift in evaluation methods for chip design. Three-dimensional (3D) electromagnetic (EM) simulations become computationally intractable as model size increases owing to the exponential growth in computation time. To address this challenge, we develop a technique that analyzes the circuit parameters of large-scale superconducting qubit chips by combining S-parameters simulated in smaller-scale 3D EM models. Herein, we design a four-qubit unit cell for large-scale qubit devices and evaluate both residual qubit-qubit coupling and control-line-to-qubit crosstalk for distant qubit pairs. In addition, we propose guard structures around qubits to mitigate nearestneighbor crosstalk. Although previous methods are limited to chips with at most ten qubits, our approach enables the analysis of systems with over a hundred qubits.