System-in-Package Doherty Power Amplifier using Hybrid LDMOS/GaN line-up for 5G Macro Driver Applications

This paper presents a compact hybrid LDMOS/GaN Doherty Power Amplifier (DPA) module targeting B1-B3 bands (1.805GHz-2.170GHz). To meet the 5G wide signal bandwidth requirements, this integrated multistage device uses 5V LDMOS as driver stage together with 48V GaN as final stage. This device is designed for driver applications, targeting high linearity at deep back-off operation (13dB from P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</inf>), thus a 2-way symmetrical Doherty architecture is selected. The measured DPA delivers an output power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</inf>) higher than 46.7dBm and a linear gain of 33.5dB. At 33.5dBm average output power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">av</inf>), the device shows excellent linearity performances. The adjacent channel power ratio (ACPR) after digital predistortion (DPD) is measured at -56.1dBc for 200MHz instantaneous bandwidth (IBW) and up to -54.6dBc for 400MHz IBW.

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Publication Details

Published
2025-06-15
DOI
https://doi.org/10.1109/ims40360.2025.11103867
Primary Topic
Advanced Power Amplifier Design
Type
article
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article

System-in-Package Doherty Power Amplifier using Hybrid LDMOS/GaN line-up for 5G Macro Driver Applications

Alexis Courty, Mariano Ercoli, Walid Rili, Christophe Quindroit et al.
Advanced Power Amplifier Design
article

System-in-Package Doherty Power Amplifier using Hybrid LDMOS/GaN line-up for 5G Macro Driver Applications

Alexis Courty, Mariano Ercoli, Walid Rili, Christophe Quindroit, Kaisseh Houssein, Stephan Maroldt
article en

Abstract

This paper presents a compact hybrid LDMOS/GaN Doherty Power Amplifier (DPA) module targeting B1-B3 bands (1.805GHz-2.170GHz). To meet the 5G wide signal bandwidth requirements, this integrated multistage device uses 5V LDMOS as driver stage together with 48V GaN as final stage. This device is designed for driver applications, targeting high linearity at deep back-off operation (13dB from P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</inf>), thus a 2-way symmetrical Doherty architecture is selected. The measured DPA delivers an output power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3dB</inf>) higher than 46.7dBm and a linear gain of 33.5dB. At 33.5dBm average output power (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">av</inf>), the device shows excellent linearity performances. The adjacent channel power ratio (ACPR) after digital predistortion (DPD) is measured at -56.1dBc for 200MHz instantaneous bandwidth (IBW) and up to -54.6dBc for 400MHz IBW.

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Advanced Power Amplifier Design
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