ITE-PBA: A Framework for SMT Solving with If-Then-Else Terms Control Flow and Parallel Branching Assignment in Formal Verification

Formal verification has become increasingly challenging as integrated circuits continue to grow in complexity. This approach translates hardware description languages into Satisfiability Modulo Theories (SMT) formulas and employs existing SMT solvers for verification. However, current hardware formal verification methodologies typically treat these solvers only as back-end components, which often fails to capture underlying information, thus limiting their performances. To address the concern, this paper introduces ITE-PBA, a novel framework that enhances SMT solving by leveraging If-Then-Else terms originating from data selectors and exploiting their embedded control flow information. In addition, a parallel branching assignment strategy simultaneously applies multiple mainstream and classical assignment schemes, improving the likelihood of identifying effective solutions. Experimental results reveal that integrating ITE-PBA into the Yices2 solver yields speedups of 9.46×.