Leveraging Steiner Tree Grid Segment in GNN for VLSI Pre-Routing Congestion Prediction
Congestion problem is the most critical issue that the very large scale integration (VLSI) industry has to face during physical design. Modern placement and routing tools often optimize performance based on congestion conditions. An accurate congestion prediction model can effectively enhance the quality of placement and routing to effectively reduce the number of time-consuming and computationally-intensive iterations. In this paper, based on the Steiner Tree graph structure, we design a new graph node, GSegment, and propose a Graph Neural Network-Based model, STGSG, for binary classification of the routing overflow congestion. Experimental results on real-world designs demonstrate that, compared to the model without using GSegment, our model has an approximately 23% improvement in the F1 score. The experiments proved the key influence of the routing probability calculation based on GSegment on the classification performance. Our dataset and code can be obtained at https://github.com/pxgh02/STGSG.
Authors
- Xiaoxu Cheng (ORCID: https://orcid.org/0000-0002-9690-1801)
- Shaokun Liu (ORCID: https://orcid.org/0000-0002-7172-0633)
- Xuan Peng (ORCID: https://orcid.org/0000-0003-3220-7957)
- Yi Zou (ORCID: https://orcid.org/0000-0002-4382-4670)
- X. Chen (ORCID: https://orcid.org/0009-0005-5119-8111)
- Xianfeng Song (ORCID: https://orcid.org/0000-0001-6871-8199)
- Yiqiu Liu (ORCID: https://orcid.org/0000-0002-7575-1533)
Institutions
- CE Technologies (United Kingdom) (GB)
- South China University of Technology (CN)
Publication Details
- Published
- 2025-05-09
- DOI
- https://doi.org/10.1109/iseda65950.2025.11100984
- Primary Topic
- Interconnection Networks and Systems
- Type
- article
- Field-Weighted Citation Impact
- 0.00