A D-Band $\times 15$ Frequency Multiplier Chain in 45 NM SiGe BiCMOS for Board-Level Packaged Array Applications

This paper presents a D-band frequency multiplier chain in 45 nm SiGe BiCMOS technology. It achieves a high multiplication factor of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 5}$</tex> for large multi-chip packaged array applications. The design consists of a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\times 5$</tex> low-frequency multiplier, an interstage buffer, and a D-band tripler that directly drives the 50 ohm load. The bandwidth extension technique is applied with an electrically coupled transformer and a harmonic filter is implemented between the cascode transistors of the tripler to enhance the harmonic rejection ratio. The frequency multiplier chain operates from 123 GHz to 136 GHz with a saturated output power (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text {sat }}$</tex>) of 1.1 dBm, a conversion gain of 2.9 dB, and a harmonic rejection ratio between 19.8 dB and 22 dB. The total DC power consumption of the design is 80 mW.