AnaSizeCoder: Code Generator for Analog Integrated Circuit Sizing Automation via Large Language Model

This study proposes a task-driven approach AnaSizeCoder that utilizes the large language model (LLM) Qwen2.5 to automatically generate optimization code for transistor sizing in analog integrated circuits (IC). Traditional optimization techniques often require manual code adjustments when faced with different optimization objectives and constraints, limiting their flexibility and efficiency in complex design tasks. To address this issue, we fine-tuned the Qwen2.5 model using LoRA (Low-Rank Adaptation) technology, enabling it to generate high-quality optimization code based on user-provided natural language requirements. We constructed a dataset comprising user requirements, summarized information, and corresponding optimization code, and consolidated all data for fine-tuning. The model was trained on 3 analog circuits, covering different optimization goals and constraints. Experimental results show that the fine-tuned model significantly improves code generation accuracy, with the best performance observed at the 4th training epoch (Epoch 4). In terms of generating summarized information, the accuracy reached 100%, while for code generation, the accuracy was above 97% across 3 different circuits. Additionally, by implementing the LDO (Low Dropout Regulator) circuit, we validated the code generated by AnaSizeCoder can successfully run and achieve the optimal Pareto frontier. Our approach enhances the automation and efficiency of analog IC design, reduces human intervention, and accelerates the design process.