Codepath: A Performance Simulation Methodology for Multicore Network Processors

As the number of transistors on a processor chip grows, it takes a longer time to execute the simulation and iterate the architecture design. The performance of current processors is increasingly dependent on software and hardware cooperation. The network processor is a domain-specific processor widely used in routers and switches. Unlike general-purpose processors, network processors need to perform a lot of table lookup operations and execute microcode programs based on the table lookup results, which has a significant impact on chip performance. To speed up the simulation for network processors, we present a performance simulation methodology called codepath. It takes into account the characteristics of realistic network software and simulates the various behaviors of the packets reasonably at a certain abstract level. Compared to RTL (Register Transfer Level) simulation, it can speed up simulations by one or two orders of magnitude and the average simulation error of packet bandwidth is only 7.36%. The manpower investment can be reduced by 85% for the first version development.