A 110-130-GHz, Frequency Quadrupler with 12.5% Drain Efficiency in 22-nm FD-SOI CMOS

A high-efficiency frequency quadrupler (X4) operates between 110 and 130 GHz. The design consists of two push-pull doublers and three differential amplifiers that improve output power and conversion gain. An extended-drain field-effect transistor (ED-FET), available in a 22-nm FD-SOI CMOS technology, is used to increase the supply voltage to 1.4 V, achieving a peak measured output power of 11.3 dBm with 12.5% drain efficiency and 6.1 dB peak conversion gain. To our knowledge, this is the highest output power and drain efficiency for silicon-based D-Band frequency multipliers.

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Published
2025-06-15
DOI
https://doi.org/10.1109/ims40360.2025.11103954
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
Field-Weighted Citation Impact
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article

A 110-130-GHz, Frequency Quadrupler with 12.5% Drain Efficiency in 22-nm FD-SOI CMOS

James F. Buckwalter, Jeff Shih-Chieh Chien, Justin J. Kim
1 links
Radio Frequency Integrated Circuit Design
article

A 110-130-GHz, Frequency Quadrupler with 12.5% Drain Efficiency in 22-nm FD-SOI CMOS

James F. Buckwalter, Jeff Shih-Chieh Chien, Justin J. Kim
article en

Abstract

A high-efficiency frequency quadrupler (X4) operates between 110 and 130 GHz. The design consists of two push-pull doublers and three differential amplifiers that improve output power and conversion gain. An extended-drain field-effect transistor (ED-FET), available in a 22-nm FD-SOI CMOS technology, is used to increase the supply voltage to 1.4 V, achieving a peak measured output power of 11.3 dBm with 12.5% drain efficiency and 6.1 dB peak conversion gain. To our knowledge, this is the highest output power and drain efficiency for silicon-based D-Band frequency multipliers.

University of California, Santa Barbara (US), Samsung (United States) (US)
National Science Foundation
Affordable and clean energy
Openalex Percentile: Top 81%
Radio Frequency Integrated Circuit Design
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