A 110-130-GHz, Frequency Quadrupler with 12.5% Drain Efficiency in 22-nm FD-SOI CMOS
A high-efficiency frequency quadrupler (X4) operates between 110 and 130 GHz. The design consists of two push-pull doublers and three differential amplifiers that improve output power and conversion gain. An extended-drain field-effect transistor (ED-FET), available in a 22-nm FD-SOI CMOS technology, is used to increase the supply voltage to 1.4 V, achieving a peak measured output power of 11.3 dBm with 12.5% drain efficiency and 6.1 dB peak conversion gain. To our knowledge, this is the highest output power and drain efficiency for silicon-based D-Band frequency multipliers.
Authors
- James F. Buckwalter (ORCID: https://orcid.org/0000-0002-9390-0897)
- Jeff Shih-Chieh Chien (ORCID: https://orcid.org/0000-0001-7077-6910)
- Justin J. Kim (ORCID: https://orcid.org/0009-0007-3203-7165)
Institutions
- University of California, Santa Barbara (US)
- Samsung (United States) (US)
Publication Details
- Published
- 2025-06-15
- DOI
- https://doi.org/10.1109/ims40360.2025.11103954
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Science Foundation