Characterization Approaches to Reduce Process Variation Dependencies for on-Wafer Power Calibration Transfer Devices in Bi/CMOS Technologies

In this contribution we present characterization strategies to reduce the impact of technology process variation in square-law detectors to be used as on-wafer power calibration transfer devices. Two standard devices included in the classical offering of Silicon based technologies are considered, i.e., junction diodes and nMOS, respectively. The power calibration transfer devices are first characterized for their responsivity using different temperature settings, enabling to generate a large set of device responses from a limited number of device samples. We then propose to employ the ratio of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2^{\text {nd }}$</tex> order to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1^{\text {st }}$</tex> order derivate of the current versus the control voltage as the pointer to identify the responsivity value to use in the calibration transfer process. The combination of a large sample base look up table with an accurate pointer allows to reduce the impact of process variations in the power calibration transfer process. The approach is then validated for both Bipolar (SiGe 130 nm) and CMOS (22 nm FD-SOI) technologies in the WR10 band.