A 132 GHz SiGe BiCMOS Sampler for Linear Front-Ends

A linear sampler with integrated clock amplifier is demonstrated in a SiGe BiCMOS process with an <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$f_{T}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{4 0 0}$</tex> GHz. The track and hold (T/H) core employs a switched emitter follower (SEF) topology with asymmetrically-sized MOSFET switches and has a track-mode bandwidth of 105 GHz, including the input and output buffers. The measured hold-mode isolation is over 20 dB up to 110 GHz. A SFDR of 43.54 dB was measured for <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$11 \text{GHz}, 0.3 V_{p p}$</tex> per side sinusoidal inputs sampled with a 132 GHz clock signal, the highest reported for a silicon sampler. Equipment-limited operation with 192GBaud NRZ and 128GBaud PAM-4 input signals sampled by 96 GHz and 64 GHz clock signals, respectively, is also demonstrated, producing NRZ and PAM-4 outputs with expanded eye openings at 96 GBaud and 64 GBaud, respectively, as required for implementation of the 1-to-2 analog demultiplexer function. The circuit consumes 235 mW from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.8 ~\mathrm{V}, 2.1 ~\mathrm{V}$</tex> and 2.5 V supplies.