Comparison of Wideband Low-Power H-Band Frequency Doublers with and Without a Driving Stage in 22 NM FDSOI CMOS

This paper presents a comparison of two low-power wideband frequency doublers operating above 220 GHz fabricated in a 22 nm FDSOI CMOS technology: chip 1 is a driverless frequency doubler; chip 2 integrates a pre-driver followed by a frequency doubler. The doubler core used in both chips is based on a pseudo-differential common source topology. The standalone doubler (chip 1) achieves a low measured conversion loss of 6.1 dB at 254 GHz. Along with a low DC power consumption <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\text{DC}}$</tex> of 12.4 mW at a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{P}_{\text {sat }}$</tex> of 0.2 dBm, this amounts to an outstanding power efficiency <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\eta_{\text {tot }}$</tex> of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{5. 6 \%}$</tex>. Additionally, the circuit occupies a minimal active chip area of only <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.046 ~\text{mm}^{2}$</tex>. To the best of the authors' knowledge, this is the highest reported efficiency for a doubler in the frequency range above 200 GHz in advanced CMOS nodes. In addition to this, the second chip with a driver amplifier (chip 2) achieves a conversion gain (CG) of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{3. 4 ~ d B}$</tex> and an efficiency of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{2. 2 \%}$</tex>. Both chips achieve a very good 3 dB bandwidth in excess of 24 %.