IncreDFlip: Incremental Dataflow-Driven Macro Flipping for Efficient Macro Placement Refinement

Macro flipping is a simple yet effective action for improving wirelength and timing during chip floorplanning. However, in modern macro or mixed-size placers, flipping is often just one tool among many in a broad toolkit aimed at optimizing wirelength within certain thresholds. This approach has created an expansive search space due to the growing number of macros, leading to less-than-ideal macro placement outcomes because the significance of macro flipping is frequently underestimated. In this paper, we highlight the importance of incremental macro flipping and introduce IncreDFlip, a methodology that leverages dataflow information to narrow the search space and utilizes dataflow decomposition from the synthesized netlist to guide flipping decisions. Drawing inspiration from human floorplanning strategies, we further propose fine-tuning techniques to enhance dataflow-driven flipping actions. The combined approach achieves an average improvement of 4.87% in total routed wirelength compared to non-flipped macro placement results, outperforming flipping actions in state-of-the-art macro and mixed-size placers, including DREAMPlace 4.1 [1], AutoDMP [2], and a commercial tool by 5.03%, 4.48%, and 2.06%, respectively. Additionally, it offers a 4.30% improvement in routed wirelength over the flipping-aware dataflow-driven placer, Hier-Rtlmp [3]. Furthermore, our method delivers an average improvement of 14.00% in worst negative slack (WNS) and 32.48% in total negative slack (TNS) after routing, along with a 43.59% reduction in runtime compared to Hier-Rtlmp.

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Published
2025-05-09
DOI
https://doi.org/10.1109/iseda65950.2025.11100996
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

IncreDFlip: Incremental Dataflow-Driven Macro Flipping for Efficient Macro Placement Refinement

Xinfei Guo, Xiaotian Zhao, Zixuan Li, Jiayin Chen et al.
Parallel Computing and Optimization Techniques
article

IncreDFlip: Incremental Dataflow-Driven Macro Flipping for Efficient Macro Placement Refinement

Xinfei Guo, Xiaotian Zhao, Zixuan Li, Jiayin Chen, Yichen Cai
article en

Abstract

Macro flipping is a simple yet effective action for improving wirelength and timing during chip floorplanning. However, in modern macro or mixed-size placers, flipping is often just one tool among many in a broad toolkit aimed at optimizing wirelength within certain thresholds. This approach has created an expansive search space due to the growing number of macros, leading to less-than-ideal macro placement outcomes because the significance of macro flipping is frequently underestimated. In this paper, we highlight the importance of incremental macro flipping and introduce IncreDFlip, a methodology that leverages dataflow information to narrow the search space and utilizes dataflow decomposition from the synthesized netlist to guide flipping decisions. Drawing inspiration from human floorplanning strategies, we further propose fine-tuning techniques to enhance dataflow-driven flipping actions. The combined approach achieves an average improvement of 4.87% in total routed wirelength compared to non-flipped macro placement results, outperforming flipping actions in state-of-the-art macro and mixed-size placers, including DREAMPlace 4.1 [1], AutoDMP [2], and a commercial tool by 5.03%, 4.48%, and 2.06%, respectively. Additionally, it offers a 4.30% improvement in routed wirelength over the flipping-aware dataflow-driven placer, Hier-Rtlmp [3]. Furthermore, our method delivers an average improvement of 14.00% in worst negative slack (WNS) and 32.48% in total negative slack (TNS) after routing, along with a 43.59% reduction in runtime compared to Hier-Rtlmp.

Shanghai Jiao Tong University (CN)
National Science and Technology Major Project
Openalex Percentile: Top 79%
Parallel Computing and Optimization Techniques
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IncreDFlip: Incremental Dataflow-Driven Macro Flipping for Efficient Macro Placement Refinement — Xinfei Guo, Xiaotian Zhao, et al. · (2025) | TGRS Research Map | TGRS