A Survey of Standard Cell Layout Design

Standard cells serve as fundamental building blocks in the integrated circuit (IC) design flow. The efficiency and quality of standard cell layout design have consistently been a major research focus in both academia and industry. With design-technology co-optimization (DTCO) playing an increasingly critical role in advanced technology nodes, standard cell layout design is undergoing a paradigm shift from traditional approaches to system-level optimization. In this paper, we systematically review the evolution of standard cell layout design, categorizing its development into three distinct phases: manual design era, automated design era and the design-technology (DT) co-design era. Building upon this historical framework, we first introduce the general flow of standard cell layout design during the era of manual design. This flow comprises four key stage: schematic drafting, stick diagram design, layout drafting, and physical verification. Subsequently, we analyze the core challenge in transitioning from manual to automated design: formulating the transistor placement and in-cell routing as a solvable optimization problem through constraint modeling. We then provide a comprehensive review of the methods employed in related work over the past four decades, encompassing graph-based algorithms, heuristic algorithms, constraint solvers, and AI-based methods. Finally, we delve into the emerging design paradigms of the DT co-design era, offering a perspective on the future of standard cell design. This perspective encompasses: concurrent cell-level and system-level optimization; finer-grained modeling and integrated design flows; specialized, custom cell library design and AI-assisted intelligent design.