PZTA: Accelerating Analog Circuit Sizing With A Transferable Circuit Theory-Inspired Pole-Zero Transient Assertion System

Transient simulation is a major computational bottleneck in analog circuit sizing optimization, especially when the circuit is unstable. Simulation-based methods achieve high accuracy but suffer from inefficiency, while surrogate-based approaches promise speedups but struggle with prediction errors and high computational costs. Challenges like poor transferability and reliability constrain their efficacy in accelerating the circuit sizing process. In this paper, we propose an optimization strategy with a transferable pole-zero-based transient assertion (PZTA) system. Inspired by transient analysis theory, the PZTA system is applicable across different topologies and effectively prunes unnecessary simulations with high accuracy. We design an offline-trained neural network model that incorporates circuit theory-inspired features, accurately asserting inferior circuit transient behavior in a zero-shot manner and adaptable to multiple optimization algorithms. Experimental results demonstrate that PZTA system effectively transfers across topologies and prunes over 83.87% of transient simulations exhibiting unstable behavior or inferior performance, with less than 1% false alarms. Our optimizers PZTA-M and PZTA-G on average reduce runtime by 49.54%.