Interleave Lock: An SAT Attack Resistant Logic Lock for Logic Circuits

The logic locking is an active protection method of logic circuits. The interlock was designed to resist the Boolean Satisfiability (SAT) attacks. However, it consumes relatively high area, delay and power overheads. In this work, a lightweight logic lock, which is named as the interleave lock, is designed. It combines the logic obfuscation and the local routing obfuscation into a switch box, and it interleaves the switch boxes into the routing obfuscation block. Furthermore, the embedding rules of the routing obfuscation blocks are proposed to increase the number of paths to be predicted in the Cyc-SAT attack. The simulation results on benchmark circuits show that, the proposed interleave lock is effective to resist the Cyc-SAT attacks. And the area, delay and power overheads are only 5.89%, 2.49% and 4.64% of that of the interlock on average respectively.