An Analytical Electrical-Thermal Coupling Model for TSV with Non-Uniform Substrate Temperature

Abstract—In three-dimensional integrated circuits (3-D ICs), the non-uniform thermal distribution in the substrate of the through silicon via (TSV) layer affects the temperature distribution of TSV, thereby impacting the interconnect performance significantly. This paper proposes a new analytical steady-state electrical-thermal coupling model for TSV in 3-D ICs and introduces a linear damping technique to improve the iterative solution algorithm for electrical-thermal coupling simulation. The proposed model supports the input of linearly and exponentially distributed substrate temperatures, allowing for the analysis of how non-uniform substrate temperature influences the thermal distribution of TSV. The model is validated by the finite element method (FEM). The results show that the proposed analytical model achieves high accuracy, with a maximum relative error of 0.7 %. Furthermore, compared with the FEM, the simulation time is reduced to less than 1 %. Moreover, this paper constructs a method of combining the electrical-thermal coupling tool with the analytical TSV model to accurately obtain the top and bottom surface temperatures of the TSV. The relative error of the simulated results compared to the FEM is less than 1%.