HDPlacer: A Hierarchy and Dataflow-Aware Macro Placer for Modern SoCs

As modern System-On-Chip (SoC) designs incorporate increasing heterogeneous macros, an effective RTL-aware macro placement method becomes crucial for optimizing design performance. This paper presents HDPlacer, a novel macro placement framework incorporating design hierarchy and dataflow relation to improve placement quality. We first construct a hierarchy tree and introduce a hierarchy-aware clustering method to effectively extract logical information and dataflow dependencies. Then, we employ a dataflow-aware analytical approach to determine the initial placement of clusters and a simulated annealing (SA)-based optimization to assign preferred regions for clusters. Finally, we develop a comprehensive analytical-based global placement with dataflow-aware net weighting and differentiable region guidance formulation, in which nets are systematically classified and assigned adaptive weights to enhance modularity and minimize critical path delays. Experimental results on ICCAD 2015 contest benchmarks demonstrate that HDPlacer achieves superior placement quality compared to the state-of-the-art placers RePlAce and Hier-Rtlmp.