OSCC-SA: Detecting Oscillation in Strongly Connected Components Using Static Analysis

Combinational logic loops present critical design challenges by inducing signal contention and sustained oscillations, leading to excessive power dissipation and functional anomalies in integrated circuits. Prior methods have primarily focused on full condition generation for potential oscillations. However, these methods come with exponential complexity (O(2 ˆ n)) and often overlook the efficiency that can be gained by directly detecting oscillations, causing inefficient resource utilization. In this work, we propose OSCC-SA, an open-source static analysis framework directly detecting oscillatory behaviour in Strongly Connected Components (SCCs), the fundamental topological manifestation of combinational loops. We develop an enhanced SCC benchmark generation methodology building upon the 2024 Integrated Circuit EDA Elite Challenge dataset, incorporating comprehensive complexity metrics. Our experimental results demonstrate that the proposed loop-based reverse search algorithm achieves linear-time complexity (O(n)) across all benchmarks while maintaining 100% detection accuracy. The practical efficacy of OSCC-SA has been recognized with the first-class award at the Challenge.