Co-Placement of I/O Pins and Cells with Multi-Electrostatics Modeling

Placement is a critical step in VLSI physical design. Traditionally, I/O pins are usually placed separately from the standard cell placement, which compromises solution quality. To address this challenge, this paper proposes a novel approach by treating I/O pins as cells and integrating them into the global placement process. The placement of I/O pins is constrained by a region, and to satisfy this constraint, they are required to be placed at the boundary. To address this challenge, a multi-electrostatics model is developed for the global placement of I/O pins and cells. Following the global placement, a two-stage legalization method is proposed to address the spacing of I/Os and the overlap of I/Os with cells, respectively. The experimental results demonstrate the efficacy of the proposed approach.