ArchBot: A Labour-free Processor Architecture Design Framework via Experienced LLM
Processors are the cornerstone of computing systems, yet their design process remains highly complex and labor-intensive. Current automated architecture design methods often rely on pre-configured models, limiting flexibility and requiring extensive manual effort. Additionally, challenges such as capturing architectural knowledge, optimizing parameters within constrained simulation times, and managing complex decision-making processes further complicate the task. To address these issues, we propose ArchBot, a labor-free processor architecture design framework leveraging large language models and reinforcement learning. ArchBot integrates a curated RISC-V architecture knowledge base, RL for microarchitecture exploration, and a machine-learning-based fast simulation model to accelerate optimization. It also uses LLMs to automate design requirement analysis and task decomposition, generating gem5 code as output. Experiments demonstrate that ArchBot achieves a 95% success rate in meeting design requirements, surpassing existing frameworks and offering a novel solution for automated processor design.
Authors
- Changxu Liu (ORCID: https://orcid.org/0009-0000-0132-1461)
- Fan Yang (ORCID: https://orcid.org/0000-0003-2164-8175)
- Zihao Chen (ORCID: https://orcid.org/0000-0002-7374-5551)
- Zhuoyuan Yang (ORCID: https://orcid.org/0009-0007-7328-957X)
- Zheng Wu (ORCID: https://orcid.org/0000-0002-3661-5360)
Institutions
- Shanghai Fudan Microelectronics (China) (CN)
Publication Details
- Published
- 2025-05-09
- DOI
- https://doi.org/10.1109/iseda65950.2025.11101285
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China