CAPlace: A College Admission Parallel Detailed Placement Method for FPGAs

Placement is a time-consuming optimization step in the FPGA implementation flow. As a key component of placement, detailed placement is a widely used refinement technique, thus its efficiency plays a significant role in design closure. Parallelizing detailed placement is a common approach to speedup runtime. However, many detailed placement methods suffer from low parallel efficiency, resulting in poor runtime performance. This paper tries to solve this problem by employing a college admissions-based approach. In the proposed framework, FPGA nodes and instances are modeled as colleges and students. The placement result is optimized by parallelizing the college admission decisions and the students’ school selection decisions. Experimental results demonstrate that the proposed framework improves placement quality by 8.2% compared with simulated annealing and achieves a runtime 2.8x faster than parallel simulated annealing on 96 threads.