Adaptive Preconditioning Guided by Divergence Analysis for Enhanced VLSI Global Placement

Global placement is a critical step in modern VLSI physical design. Traditional electrostatic-based analytical placement algorithms, such as ePlace, employ a two-layer optimization loop: an inner loop using Nesterov’s gradient descent, and an outer loop updating the density penalty multiplier to progressively enhance the density penalty. However, these conventional update methods often fail to balance the optimization efforts across different nets, leading to suboptimal solutions. In this paper, we introduce an adaptive preconditioning algorithm that addresses these limitations. Our approach utilizes divergence analysis to identify clusters within the placement region, followed by net preconditioning to adjust the optimization efforts accordingly. This ensures a more balanced distribution of optimization efforts across all nets, leading to improved placement quality. Experimental results on the DAC-2012 benchmarks suite demonstrate that our algorithm achieves a reduction in final placement wirelength compared to DREAMPlace, while obtaining an optimal tradeoff between half-perimeter wirelength (HPWL) and iteration count.