A Two-Stage Optimization Framework for Logic Replication in Hypergraph Partitioning

With the explosive growth in the complexity of integrated circuit designs, hardware emulation platforms face significant challenges in simulating designs with billions of gates using a single Field-programmable Gate Array (FPGA). This paper proposes a two-phase optimization framework: first, an initial hypergraph partitioning is performed using an improved FM algorithm, followed by the application of a targeted logic replication strategy that considers the cost-effectiveness of replication on the partitioned results. By adopting the two-stage optimization strategy, our method maintains algorithmic efficiency while reducing computational complexity. Experimental results demonstrate that, compared to non-replication strategies, our approach achieves an average reduction of 17% in total hop distance while completing logic replication in a significantly shorter time, validating the effectiveness of the phased optimization strategy.