Point-Cap: An Efficient Model for Chip-Scale Interconnect Capacitance Extraction
In this paper, we present a PointNet++-based method for capacitance extraction (Point-Cap) of chip-scale interconnects with high efficiency and accuracy. By modeling the layout structure as point-cloud-like data, the process of gathering features of conductors to the net level can be done efficiently and automatically by our model and then utilized to predict precise total capacitance and coupling capacitance. Compared to the previous state-of-the-art work, GNN-Cap, Point-Cap reduces the average relative errors in the total capacitance and coupling capacitance calculations by 28.8% and 38.6%, respectively.
Authors
- Tinghuan Chen (ORCID: https://orcid.org/0000-0002-9195-6619)
- Yaohui Han (ORCID: https://orcid.org/0009-0007-2201-7283)
- Fan Yang (ORCID: https://orcid.org/0000-0003-2164-8175)
- Weizhe Zhang (ORCID: https://orcid.org/0000-0003-4783-876X)
- Qing Ye (ORCID: https://orcid.org/0000-0003-2055-218X)
- Lihao Liu (ORCID: https://orcid.org/0009-0002-6431-7392)
Institutions
- Fudan University (CN)
- Chinese University of Hong Kong, Shenzhen (CN)
- Shenzhen Academy of Aerospace Technology (CN)
Publication Details
- Published
- 2025-05-09
- DOI
- https://doi.org/10.1109/iseda65950.2025.11101143
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- Research and Development