An LSTM-Based ESL Power Prediction Model Design Optimization Method

With the increasing complexity of functionality and scale in network processing and AI chips, power has become a critical constraint in the design of future processor architectures. Therefore, accurately quantifying processor power during the early stages of design and at higher levels of abstraction is crucial. Particularly in scenarios such as network packet switching, where time-series feature dependencies are significant, fully exploiting and utilizing temporal correlations can significantly enhance power prediction performance. This article proposes an ESL power prediction model that extracts key features from ESL model simulations and architectural design parameters, combined with a Long Short-Term Memory (LSTM) to construct an architecture-level power prediction model. Validation was performed on high-throughput network switching chips. The results show that the proposed model effectively improves the accuracy of ESL power prediction, achieving an average prediction error of less than 5% for both component-level and system-level power, with the best case reaching as low as 1.8%.