CNTFET-based efficient Ternary adder for low power applications

The rapid growth of digital devices demands innovative solutions for low-power, high-efficiency computing systems. Ternary logic presents a capable substitute to traditional binary system in VLSI design, offering benefits such as fewer interconnects, faster operation, and reduced chip size. Carbon Nanotube Field-Effect Transistors (CNTFETs) have emerged as a promising alternative to traditional CMOS technology, offering superior performance at reduced power levels. This research implements a ternary half adder using CNTFETs, targeting low-power applications. Unlike conventional binary adders, ternary adders operate with three logic states, enabling enhanced data density and lower power dissipation. By leveraging the unique electrical characteristics of CNTFETs, including high mobility and tunable threshold voltages, the proposed ternary adder achieves significant improvements in power efficiency and delay reduction. The designs combine advanced ternary and traditional binary logic approaches. These circuits underwent extensive HSPICE simulations to measure power consumption, delay, noise, and power delay product. The performance of these circuits is evaluated against alternative designs from recent publications. The proposed ternary half adder demonstrates 90% improvements in power consumption and 52% in noise margin. The proposed ternary adder design showcases CNTFETs' potential for scalable, power-efficient multi-valued logic circuits, paving the way for advancements in high-performance digital arithmetic.