Design of Gain-Variable AFE Circuit for 32Gbps SerDes

This paper presents a 12nm FinFET-based 32Gbps analog front-end (AFE) with adjustable gain, focusing on the design and optimization of a continuous-time linear equalizer (CTLE). The AFE consists of an attenuator (ATT), a CTLE, and a two-stage variable gain amplifier (VGA). The ATT attenuates low-frequency signals and fine-tunes the frequency-domain waveform, while the CTLE enhances high-frequency gain and bandwidth through shunt peaking and negative capacitance techniques. The VGA amplifies low-frequency signals and provides gain adjustability. Post-layout simulation results demonstrate that under a 32dB channel loss, the equalized eye diagram achieves an eye opening of 0.86UI and an eye height of 548mV, indicating excellent equalization performance. Furthermore, the circuit incorporates tunable resistors and capacitors to adapt to various channel conditions, showcasing high flexibility and practicality. This paper combines shunt-peaking with negative transconductance-based positive feedback techniques and introduces an ATT module for signal preprocessing, effectively enhancing high-frequency compensation performance and providing a reliable solution for high-speed data transmission.