A 50MS/s 16-bit three-stage high-precision Digital- to-Analog Converter

This paper presents a 50MS/s 16-bit current-steering digital to analog converter (DAC) using three-stage decoding. A recursive decoding method is proposed to reduce the number of logic gates used. Based on the structure of cascode current mirror, a current source output impedance enhancement circuit is proposed to increase the accuracy of the current. In addition, a calibration technique based on a successive approximation loop, including a comparator, a multiplexer, and a calibrated DAC. Using tsmc180nm process, this design achieves >75.5 dB spurious-free-dynamic-range (SFDR) at 1.61 MHz input rate and >61.8 dB SFDR over the Nyquist bandwidth. And the differential nonlinearity (DNL) is within ±0.32 LSB, while the integral nonlinearity (INL) is less than ±0.32 LSB.