28-nm FD-SOI CMOS Power Amplifier with Stacked-FET Structure to Enhance Output Power for 5G FR2 Applications

In this study, we design a CMOS power amplifier for 5G FR2 applications. In order to overcome the low breakdown voltage of the CMOS and obtain high output power, a power stage is designed using a stacked-FET structure. Thus, the power stage consists of a common-source transistor and a stacked transistor. The driver stage is designed with a common-source structure to reduce the supply voltage for the driver stage, thereby suppressing the dc power consumption at the driver stage. The power amplifier is designed with a differential structure to easily obtain ac ground through virtual ground. In particular, the power amplifier is designed with a 28-nm FD-SOI CMOS process to mitigate power loss caused by transformers, inductors, and metal lines. The operating frequencies of the designed power amplifier range from 27 GHz to 30 GHz. Output 1-dB compression point (P<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</inf>) in the corresponding operating frequency range is from 18.3 dBm to 18.9 dBm. Also, the power added efficiency (PAE) in the corresponding operating frequency range is from 40.1% to 40.9%. The chip size including the test pads is 0.84 × 0.66 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the core size is 0.56 × 0.16 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.