Design of a Time-to-Digital Converter and Calibration Circuit Based on FPGA

This paper presents a high-resolution time-to-digital converter (TDC) implemented on FPGA. The design combines the direct counting method with a tapped delay line architecture, and incorporates a dual-clock sampling technique to calibrate timing skews in FPGA internal signals. Experimental results demonstrate that the proposed TDC achieves a timing resolution of 14ps.