Design of K/Ka Band 31.5dB Single-Ended Variable Attenuator Using 65-nm RFCMOS Process for Satellite Communication Systems

In this study, we design a K/Ka band 31.5 dB attenuator using a 65-nm RFCMOS process. To reduce insertion loss and phase error, a combination of distributed-type, T-type, and π-type structures is adopted. In order to optimize the performance in the pass mode and the attenuation mode, the gate width of the transistor is optimized. The capacitor phase compensation technique is applied to suppress the signal phase error between the pass mode and the attenuation mode. The target operating frequency is set from 14 GHz to 32 GHz. In the target operating frequency range, the insertion loss of the pass mode is suppressed to be less than 5.48 dB. In addition, the RMS attenuation error and RMS phase error are lower than 0.14 dB and 2.59°, respectively. The chip size including the test pads is 0.450×0.440 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, and the core size is 0.282×0.100 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.