An Energy-Efficient SAR ADC with an Improved Switching Strategy

This article improves the traditional SAR ADC energy-saving switching strategy and proposes a low-power SAR ADC with 10 bits and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20 \text{kS} / \mathrm{s}$</tex>. Firstly, behavioral modeling and validation of the switching process were conducted on MATLAB, resulting in an average conversion energy of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7.9 \text{CV}_{\text {ref }}{ }^{2}$</tex> and an average reset energy of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$15.85 \text{CV}_{\text {ref }}{ }^{2}$</tex>, saving 98.26 % of conversion energy compared to traditional switching strategies. Using TSMC 65 nm technology for circuit construction and simulation, when the supply voltage is 1 V, the simulation results of each indicator as SNDR is 60.66 dB, SFDR is 72.55 dB, ENOB is 9.78 bits, and the total power consumption of the system is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2 \mu \mathrm{W}$</tex>.