A 14.1 GHz-to-30.5 GHz Dual-mode VCO with Transformer-Switching and Current-Reuse Dynamic Body-Biasing Technique in 55-nm CMOS

A single-core dual-mode voltage-controlled oscillator (VCO) with wide tuning range and low power consumption is proposed in this paper. Through the integration of current-reuse structure and dynamic body-biasing, the Current-Reuse Dynamic Body-Biasing Technique (CRDBB) consumes much lower power. Additionally, a switchable transformer and 4-bit switched capacitor array are incorporated into the VCO's LC resonator to maximize the tuning range (TR). Implemented in SMIC 55-nm 1P8M CMOS process, the VCO has a core area of 0.063mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Simulation results show that the frequency ranges from 14.1 to 30.5 GHz, achieving a TR of 73.5% and with power consumption ranging from 6.9 to 11.2 mW from a supply voltage of 1.2 V. The phase noise (PN) at 1 MHz offset is between -113.5 dBc/Hz and -102.1 dBc/Hz, with a figure- of-merit (FOM) ranging from 181.3 dBc to 188.1 dBc/Hz.

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Published
2025-05-23
DOI
https://doi.org/10.1109/ecie65947.2025.11087099
Primary Topic
Radio Frequency Integrated Circuit Design
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article
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article

A 14.1 GHz-to-30.5 GHz Dual-mode VCO with Transformer-Switching and Current-Reuse Dynamic Body-Biasing Technique in 55-nm CMOS

Bingnuo Li, Xiaoying Deng, Liangping Luo, Weichao Hu
Radio Frequency Integrated Circuit Design
article

A 14.1 GHz-to-30.5 GHz Dual-mode VCO with Transformer-Switching and Current-Reuse Dynamic Body-Biasing Technique in 55-nm CMOS

Bingnuo Li, Xiaoying Deng, Liangping Luo, Weichao Hu
article en

Abstract

A single-core dual-mode voltage-controlled oscillator (VCO) with wide tuning range and low power consumption is proposed in this paper. Through the integration of current-reuse structure and dynamic body-biasing, the Current-Reuse Dynamic Body-Biasing Technique (CRDBB) consumes much lower power. Additionally, a switchable transformer and 4-bit switched capacitor array are incorporated into the VCO's LC resonator to maximize the tuning range (TR). Implemented in SMIC 55-nm 1P8M CMOS process, the VCO has a core area of 0.063mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Simulation results show that the frequency ranges from 14.1 to 30.5 GHz, achieving a TR of 73.5% and with power consumption ranging from 6.9 to 11.2 mW from a supply voltage of 1.2 V. The phase noise (PN) at 1 MHz offset is between -113.5 dBc/Hz and -102.1 dBc/Hz, with a figure- of-merit (FOM) ranging from 181.3 dBc to 188.1 dBc/Hz.

Hsin Sheng College of Medical Care and Management (TW), Shendi University (SD), China Shenhua Energy (China) (CN)
Affordable and clean energy
Openalex Percentile: Top 82%
Radio Frequency Integrated Circuit Design
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