Performance Analysis of FPGA-Based Multipliers for Image Multiplication

Efficient multiplication is a critical operation in many image-processing applications, particularly in FPGA-based hardware acceleration, where optimized arithmetic units play a key role in achieving high performance. This paper presents a comprehensive performance analysis of different multipliers, including Array, Vedic, Modified Booth, and Wallace, specifically for FPGA implementation. The evaluation considers essential design metrics such as area utilization (LUTs), power consumption, delay, area-delay product (ADP), and power-delay product (PDP), ensuring a thorough comparison of their efficiency. The multipliers are designed, implemented, and analyzed using Vivado Vitis HLS and the PYNQ framework, with experiments conducted on the PYNQ-Z2 board to assess real-world applicability. Furthermore, the study extends to image multiplication, where the performance of different multipliers is examined in the context of real-time image processing tasks. By analyzing computation speed, resource efficiency, and power consumption, the results highlight critical trade-offs that influence the selection of an optimal multiplier for FPGA-based image processing applications. The insights gained from this study contribute to the ongoing advancement of high-performance, energy-efficient hardware acceleration techniques, helping to optimize FPGA-based systems for real-time image processing applications.