Design and Analysis of a Radix-4 Booth Multiplier with Approximate Computing and Sparsity Adaptation for Convolutional Neural Network Acceleration

Efficient hardware multipliers are essential in VLSI systems, especially for compute-intensive tasks such as digital signal processing, image processing, and deep learning accelerators. However, conventional multiplier architectures often suffer from high power consumption, long propagation delay, and inefficient memory access, limiting their applicability in high-performance computing systems. Existing Radix-4 Booth multipliers and CNN accelerators typically face challenges in achieving low power and high-speed performance due to unoptimized partial product handling and redundant computations. To overcome these limitations, this work proposes an optimized pipelined Radix-4 Booth multiplier architecture tailored for FPGA-based CNN acceleration. The design employs approximate partial product row addition to reduce hardware complexity and delay, while ensuring computational accuracy. It also introduces memory access optimizations and a dynamic sparsity adaptation mechanism that effectively skips redundant operations, improving both power and resource efficiency. Additionally, deep pipelining and clock gating techniques are integrated to enhance timing and reduce idle power. Synthesized in Verilog and implemented using Xilinx Vivado, the proposed design demonstrates significant improvements in speed, power efficiency, and hardware utilization compared to conventional approaches.